High performance phase-locked loops (PLLs) are widely used in a variety of applications. For example, a PLL may be used in a wireless communication system to provide a low-noise local oscillation (LO) signal for up-conversion and down-conversion. A PLL is a negative feedback loop in which the phase of a feedback signal derived from an output signal is forced to follow that of a reference signal. The basic modern PLL may include a reference source, a phase detector (PD), a charge pump (CP), a loop filter (LF), and a voltage controlled oscillator (VCO). When a frequency divider is placed between the VCO and the PD, the PLL may be regarded as a frequency synthesizer where the frequency of the VCO output may be an integer multiple or a non-integer multiple of that of the reference signal. Unlike an integer-N PLL, a fractional-N PLL can achieve a frequency step much smaller than its reference signal and still maintain reasonably high reference frequency. However, the fractional control module used in a fractional-N PLL produces quantization phase error (which is also referred to as quantization noise for simplicity) and thus results in spurs at the VCO output, which deteriorates the spectral purity of the synthesized signal.
A typical fractional-N PLL may employ a sigma-delta (ΣΔ) modulator as the fractional control module to dynamically control a division ratio used by the frequency divider placed between the VCO and the PD. The fractional-N frequency division is achieved through division-ratio averaging. Specifically, an integer frequency divider is used, but the division ratio is dynamically switched between two or more integer values. The instantaneous division ratio of the frequency divider can only be an integer value, but the long-term average of the division ratio is a non-integer value. As a result, the instantaneous phase error appearing at the input of the PD is not always zero due to the quantization noise. This phase error modulates the tuning of the VCO and thus creates spurious tones at the VCO output.
Though the loop bandwidth of the PLL can be reduced to reduce the quantization noise and spurs resulting from the fractional control module (e.g., ΣΔ modulator), it is highly desirable to increase the loop bandwidth of the PLL to reduce the VCO noise and to speed up the lock time for certain applications. Thus, there is a need for an innovative PLL with wide loop bandwidth and quantization noise cancellation.